Good Timing

In my last retrochallenge post I reported difficulty latching the address bus. Using the logic analyzer, I saw the latch signal was coming a but too late relative to the hold time of the address bus. I needed a way to edge trigger a shorter pulse. I found this handy circuit which creates a positive edge triggered pulse.

The pulse width is set by the RC time constant. I selected the resistor value to limit the current being sourced and sunk by the NAND gate (configured as an inverter). A value of 390 ohms limits the current to 13 mA peak, which is a 50% derating on the 25 mA absolute max allowed value for a LS74HCT00 device. The current spikes are short as they charge/discharge a small capacitor of a couple hundred pF to set the pulse width to 140 ns. I picked the cap somewhat by trial and error. The resulting timing looks like this:

The LE_D signal triggers the pulse generator, which outputs LE_A. The LE_A signal successfully latches the address before it changes right after the falling edge of phi2. 

Fortunately, I was able to use spare NAND and AND gates and only had to add the two passives. Almost free! Being able to latch the address allows the Atari handler and MCU software to be written to use a command/data protocol. The address specifies the command and the data shows up on the bus. I wonder what is possible with such an interface.