Friday, June 14, 2019

Good Timing

In my last retrochallenge post I reported difficulty latching the address bus. Using the logic analyzer, I saw the latch signal was coming a but too late relative to the hold time of the address bus. I needed a way to edge trigger a shorter pulse. I found this handy circuit which creates a positive edge triggered pulse.

The pulse width is set by the RC time constant. I selected the resistor value to limit the current being sourced and sunk by the NAND gate (configured as an inverter). A value of 390 ohms limits the current to 13 mA peak, which is a 50% derating on the 25 mA absolute max allowed value for a LS74HCT00 device. The current spikes are short as they charge/discharge a small capacitor of a couple hundred pF to set the pulse width to 140 ns. I picked the cap somewhat by trial and error. The resulting timing looks like this:

The LE_D signal triggers the pulse generator, which outputs LE_A. The LE_A signal successfully latches the address before it changes right after the falling edge of phi2. 

Fortunately, I was able to use spare NAND and AND gates and only had to add the two passives. Almost free! Being able to latch the address allows the Atari handler and MCU software to be written to use a command/data protocol. The address specifies the command and the data shows up on the bus. I wonder what is possible with such an interface.

Friday, April 5, 2019

Retrochallenge 0319 - Last Post

I had to take a week off of the Retrochallenge to take care of life. I finished the month by making a completed circuit on a breadboard with mostly neat wires. I ran into trouble reading the address bus. The timing is too tight, so I need to change the latch signal for the address buffer.

The Retrochallenge is a good excuse to make some progress and to share the useless tinkering of the hobby. Here's what I have to show for it:

Thanks for following along!

Friday, March 22, 2019

The Flip Flop

I'm flip flopping like a politician on the data read algorithm in the Atmega328P MCU interface to the cartridge port. As described in previous posts, I was using an edge-triggered interrupt to alert the MCU that new data was ready. I chose the interrupt method because the original design was implemented on a single ESP32 that handled both the cartridge and wifi interfaces. The handling of the two interfaces was inherently asynchronous because they were both reacting to their external counterparts. The cartridge side didn't know when the Atari would push data and likewise with wifi and remote server. This didn't work very well given my rudimentary MCU programming skills. Splitting the system into two MCU's fixed the problem. It also allows a flip-flop to be made.

Researching this project, I ran across a website from Poland (that I can't find now) on interfacing to the 6502 bus. They used an SR flip-flop to latch the write enable signal before sending it to an MCU. The MCU could then poll the signal for a state change. While the interrupt method allows for simpler decoding logic, the polling makes for simpler software. And it's faster. The interrupt takes about 3 microseconds (several 6502 clock cycles). The polling can respond in half a microsecond or about a single 6502 cycle. This will add up to many saved clock cycles on the Atari side in the end.

Here's the concept.

The LE line goes low when the 6502 performs a STA $D5xx (described in this RC2019/03 post). The LE signal SETS the SR flip flop and its output Q tells the MCU it's time to read the data and address. The read operation is described here. Note, now the time between the LE going high and the /OEDATA going low is < 1 microsecond. It used to be 3 microseconds. Then the MCU sends a RESET to the SR flip flop and goes on to its next operation ...

... which is what I'm going to do, too.

Tuesday, March 12, 2019

NOP

The architecture of my Atari cartridge port interface adapter to an ESP8266 is to use an Arduino Nano (ATmega328P MCU) as an intermediary. Another way is to use an FPGA, but that's more costly and I don't have enough experience to try that yet. Using an MCU on the cartridge port, which is really just the 6502 bus, calls for the use of 3-state latches to capture and to hold data in place while the two microprocessors go about their business. While there is a flashcart out there that uses a 32-bit STMicro MCU to respond with 6502-bus timing, I'm not confident I can do that with a 16-MHz 8-bit MCU.

I've run into several challenges. First, what DIO pins should I use? I ended up splitting the 8-bit bus into two 4-bit nybbles spread between ATmega328P Ports D and B. The Arduino doesn't have an entire 8-bit port free. Reading the port requires some fun bitmath. Second, the output enable is sent out over a pin on Port C right before the 8-bit data is read. The 16-MHz is so fast, I had to throw in a NOP instruction to properly read the data. The enable time of the SN74HCT573 (/OE->Q) is at least 40 ns. Assuming the ATmega changes its output pin state at the end of it's clock cycle and begins its read at the start of the next, there's not enough time for the latch to output its data. A single NOP on the ATmega is 62.5 ns, more than the enable time on the latch. Or, maybe the ATmega328P digital input has some setup time that's otherwise violated. Either way, some brief testing indicates no missing bits.

The third challenge is related to the second - the disable time on the latch is also at least 40 ns. I want to read the address latch and the data latch sequentially. To avoid bus contention, the second latch cannot be enabled until after the first latch is fully disabled. This problem was solved by moving some instructions around inside the interrupt routine to put some delay between the two read operations.

Here's a logic analyzer plot showing the timing:
The disable time (OED rising edge to Q0 rising edge) is much longer than expected. But the Arduino C++ interrupt code arrangement makes the timing work out:

The interrupt routines reads two bytes and increments a counter, all in less than 5 microseconds. I put the counter increment in between the two reads to give the first latch time to disable before the second latch is enabled, which avoids bus contention. Cool.

Sunday, March 10, 2019

Schematic

Worked on a schematic this weekend ahead of adding more components to the circuit. I decided to include a buffer to grab the 8-bit address when the Atari executes a STA $D5xx instruction. I figure I can use the 8-bits to add some features or make the protocol simpler.
Excerpt of the schematic showing the Atari 8-bit cartridge edge connector, address and data buses, and decoder logic.

I use the free "maker" version of Autodesk Eagle. Here are the Eagle libraries used in the design:

  • Atari 800 parts, including a cartridge board, is at AtariAge
  • Arduino Nano pinout/footprint on Github
  • NodeMCU (esp8266 board) pinout/footprint on Github.
  • 74xx-eu built-in libary. This library had the HCT logic family where the US version did not. I'm not sure that really matters, but just in case....
I am grateful to the generosity of the individuals and organizations who make the tools and information freely available for hobbyist and maker use. That makes fun hardware projects like this possible. 

Wednesday, March 6, 2019

Unintended Interrupt

Most of the time spent on a hardware project is solving problems. I ran into an interesting one on my Arduino Nano: sending a digital out high on one pin was causing the hardware interrupt on another pin to trigger. What? Turns out my test setup was causing the problem. A bad case of the observer effect.

The Nano is biased at 5 V, which makes it easy to interface to the Atari. However, my FPGA-based logic analyzer is only 3.3 V compliant, so I need a level translator in between. I'm using a small 4-bit translator based on a single-FET design. These are often used with I2C interfaces. 

I was stumped by the false interrupts and couldn't find anything like it online. It drove me to read the Atmega 328 data sheet. At least I have a better understanding of the microcontroller and its interrupts. I finally went back to something I knew worked: turn the on-board LED on and off using an external interrupt. I then started changing the output pin #, which worked until it landed on the one I was monitoring with the logic analyzer. Ack! Grasping at straws, I tried adding pull up and pull down resistors to no avail. Then I realized the false interrupts only occurred when the output changed from low to high.

Maybe translator was sinking or sourcing too much current on the Nano's push-pull output drive? The typical diagram I see with these translators show effectively open drain outputs, so maybe I'm not using it in its intended application. It also turns out these things pull current when the signal is low. I think that suddenly applying a high causes the translator to load down the output with too much current, causing a malfunction on the IO bus.

I fixed it by putting a 330-ohm resistor in series between the output and the translator.

Whew.


Saturday, March 2, 2019

Decoder

Although this is a rebuild of my early breadboard using a new microcontroller, I want to go step-by-step to make sure each part works. The first circuit is a decoder to read the bus signals and generate a latch enable (LE) and an output enable (OE') for the interface buffers I will use between the Atari and the Arduino. Here's the logic diagram:
The cartridge port has a convenient Cartridge Control (CCTL') line that was intended to be used for bank switching. CCTL' goes low with an address of $D5xx. I want to be able to latch the data bus into a buffer with 6502 executes a STA $D500. This video has a nice explanation of 6502 bus timing and this page has a write enable circuit at the bottom, both of which gave me enough background to end up with this design.

I built this up using TI HCT logic, which you can still get in DIP packages. It uses one NAND (SN74HCT00) and one AND (SN74HCT08) chip.
I connect to the cartridge port using a breakout board and monitor the signals with a FPGA board running logic analyzer firmware. To cause LE to go high, the 6502 needs to execute STA $D500. I just used a POKE command in BASIC to do this easily:
The captured signals looked like this:
Note how the clock signal PHI2 gates the LE when the CCTL and R/W are both high. The resulting signal will be used to latch the data bus into a buffer and to interrupt the Arduino.

Thanks for reading.